1. Field of the Invention
This invention relates to a semiconductor device and a method of fabrication thereof, and more particularly to a MISFET or MOSFET structure and a fabrication method thereof, wherein it is capable of contribution to the maintenance of reliability for further speeding-up MISFETs or MOSFETs and to the realization of further ultrafine devices.
2. Description of the Prior Art
In a high integration silicon integrated circuit comprising a silicon MISFET or MOSFET as a chief constituent element, balanced size reduction of elements is intended with a scaling law into consideration for the purpose of constructing a fine circuit and speeding-up circuit operation. For this, a source-drain region is also contemplated to be formed into a shallow junction.
For example, as shown in FIG. 1 which is a schematic explanatory view illustrating the structure of a prior art U-MOS, in the vicinity of the drain thereof and a flow of carriers 10, a junction configuration of the drain of the prior art U-MOS in a cross-section in the direction connecting the source to the drain is substantially flush with its side surface making contact with the gate oxide film 2 and comprises only a flat bottom surface, or is slightly protruded toward the substrate 1, and hence includes a shallow side surface having a configuration of a bowl as in the conventional MOSFETs.
The configuration is caused owing to the physics of the ion implantation process into the drain region 7 and of the thermal treatment process. For this, the flow 10 of the inversion layer carriers reaches the drain without being spread too much after the pinch-off point, as illustrated in FIG. 1. Accordingly, spreading resistance is increased and the electric field is increased to promote the hot carrier degradation.
On the other hand, the channel, which is the passage for carriers, has its thickness defined by quantum mechanics and hence is not scaled. Physical phenomena in the vicinity of the drain are therefore not necessarily scaled, so that the electric field at the drain edge is more severely concentrated because the substrate density becomes higher and additionally, the junction between the source and the drain must be shallower as the device scaling proceeds.
This promotes the impact ionization phenomena and causes lowering of reliability owing to the hot carrier deterioration. In the MISFET or MOSFET, the electric field at the drain edge is increased as the MISFET or MOSFET is made fine as described above. To overcome this difficulty, some innovation related to a device structure is needed to lower such an increased electric field.
Although electric field moderation has been successfully obtained by reducing the concentration slope at the drain edge, as in LDD-MOSFETs and gate-drain overlapped LDD-MOSFETs, this suffers from another difficulty that it is unlikely to be made fine in view of an increase of the series resistance component and structural problems as the circuit becomes finer.
In the prior art MOSFETs, the electric field at the drain edge is increased as they are made finer, and hence realization of the electric field moderation is earnestly desired with the aid of a device structural innovation without relying on methods manipulating the impurity concentration slope at the drain edge.